This invention relates to phase detection in clock data recovery applications. More particularly, this invention relates to a phase detector, for use in clock data recovery, that is predictable and stable.
It is almost axiomatic that digital systems are clocked. For a clock of period T, the clock signal is typically a series of square (or rectangular) pulses of durations T/2, separated by zero-amplitude intervals of durations T/2. Such a clock has a rate or frequency of 1/T. The clock is used to time data signals, with each data pulse having a duration T/2. However, there is no reason why consecutive data pulses need be separated by zero-amplitude intervals. Therefore, two or more (n) consecutive data pulses can be transmitted as a single continuous “high” signal of duration nT. In each clock period T, one data pulse can be transmitted. Thus, the data rate of the system is the same as that of the clock rate. In a double data rate system, data is sampled on both rising and falling clock edges, resulting in a data rate twice that of the clock rate, with each data pulse having a duration T/2.
Because any particular data pulse can be either high (“1”) or low (“0”), a train of unknown data pulses is commonly represented by two superposed waves, with the edges of the pulses are not purely vertical, so that the progression of pulses is distinctly visible. Each possible data position thus is shown as both high and low, signifying that either value is possible in a stream of actual data. Because the edges representing the pulse transitions in such a representation are not purely vertical, the intersecting inclined lines give each pulse position the appearance of an eye, and each pulse position is therefore referred to as a “data eye.”
When sampling data, it is best that the sampling occur as close as possible to the center of the data eye, as far as possible from the transitions, because sampling during a transition could provide a false reading of the data. This is relatively easy when the clock is sent along with the data. However, when the clock must be recovered from the data, clock recovery errors could make centering the sampling time in the data eye—“eye centering”—difficult or unreliable. Any such problems are compounded in a programmable logic device, where the circuit paths, as well as the clock recovery circuitry, differ from one user logic design to the next.
Clock recovery is commonly accomplished using a loop circuit—i.e., a phase-locked loop (PLL) or delay-locked loop (DLL)—in which a phase detector detects a phase variation between input and recovered signals, causing a charge pump to vary a control signal (i.e., voltage or current) of an oscillator (e.g., a voltage-controlled oscillator or current-controlled oscillator) to bring the recovered signal back into line with the input signal. Variation or ripple in the control signal may cause unacceptable jitter in the oscillator output, giving rise to clock recovery errors, thereby causing eye centering errors which in turn result in data read errors.
Known phase detectors contribute to jitter in different ways. For example, a full-rate linear phase detector, such as a Hogge phase detector, operates predictably but its performance degrades as the clock rate increases. A nonlinear phase detector such as a Bang Bang phase detector causes a large ripple on the control signal making the loop circuit output unpredictable. A half-rate linear phase detector is linear, therefore predictable, but produces a DOWN (or REFERENCE) signal having twice the pulse width of the UP (or ERROR) signal, resulting in a large ripple effect on the oscillator control signal.
It would be desirable to be able to provide a phase detection method and circuitry that minimizes jitter in a recovered clock application, thereby improving data reading.